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Ordering number : EN*5396
CMOS LSI
LC74751
On-Screen Display LSI
Preliminary Overview
The LC74751 is a CMOS LSI that supports on-screen display of characters and patterns on a TV screen under the control of a microcontroller. The LC74751 includes an on-chip character ROM that provides 128 characters in a 12 x 18 dot format. This IC supports display of up to 12 lines of 24 characters each for a maximum of 288 characters.
Package Dimensions
unit: mm 3059-DIP22S
[LC74751]
Features
* Display format: 24 characters by 12 rows * Characters displayed: Up to 288 characters * Display control ROM (line ROM): ROM for 64 lines (Control in line units: lines consisting of 24 characters) * Display RAM: 176 characters (Used for the specification of user-defined characters.) * Character format: 12 (horizontal) x 18 (vertical) dots * Characters in font: 128 * Character sizes: Four sizes each in the horizontal and vertical directions * Initial display positions: 64 horizontal positions and 64 vertical positions * Blinking: Specifiable in character units * Blinking types: -- Two periods supported: 1.0 second and 0.5 second -- Three duty types supported: 25%, 50%, and 75% * Blanking: Over the whole font (12 x 18 dots) * Background color -- 8 background colors (in internal synchronization mode): 4fsc (NTSC/PAL/PAL-M/PAL-N) -- 4 background colors (in internal synchronization mode): 2fsc (NTSC) -- Single background color (blue) (in internal synchronization mode): 2fsc (PAL/PAL-M/PAL-N) * External control input: Serial data input * Synchronizing signals: Supports switching between internal and external synchronizing signals. * On-chip sync separator circuit * Video output: Composite video output in the NTSC, PAL, PAL-M, or PAL-N format * Superimpose function: Superimposes the character output on the composite video output.
SANYO: DIP22S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
83096HA (OT) No. 5396-1/15
LC74751 Pin Assignment
Specifications
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD VIN VOUT Pd max Topr Tstg Ta = 25C VDD1 and VDD2 All input pins Conditions Ratings VSS-0.3 to VSS+7.0 VSS-0.3 to VDD+0.3 VSS-0.3 to VDD+0.3 300 -30 to +70 -40 to +125 Unit V V V mW C C
Allowable Operating Ranges
Parameter Symbol VDD1 VDD2 VIH VIL VIN1 VIN2 fOSC1 fOSC2 Oscillator frequency fOSC3 fOSC4 fOSC5 fOSC6 VDD1 VDD2 CS, SIN, RST, SCLK, and SEPIN CS, SIN, RST, SCLK, and SEPIN CVIN SYNIN Crystal oscillator pins (NTSC: 2fsc mode) Crystal oscillator pins (NTSC: 4fsc mode) Crystal oscillator pins (PAL: 4fsc mode) Crystal oscillator pins (PAL-M: 4fsc mode) Crystal oscillator pins (PAL-N: 4fsc mode) LC oscillator pin (When an LC oscillator is used) 5 Conditions Ratings min 4.5 4.5 0.8 VDD1 VSS - 0.3 2 Vp-p 2 Vp-p 7.15909 14.31818 17.73447 14.30244 14.32822 7 11 2.5 Vp-p typ 5.0 5.0 max 5.5 1.27 VDD1 VDD1 + 0.3 0.2 VDD1 Unit V V V V V V MHz MHz MHz MHz MHz MHz
Supply voltage Input high-level voltage Input low-level voltage Composite video input voltage
Electrical Characteristics at Ta = -30 to +70C, VDD1 = 5 V unless otherwise specified
Parameter Output off leakage current Output high-level voltage Output low-level voltage Input current Symbol Ileak VOH1 VOL1 IIH IIL IDD1 IDD2 CVOUT SEPOUT: VDD1 = 4.5 V, IOH = -1.0 mA SEPOUT: VDD1 = 4.5 V, IOL = 1.0 mA CS, SIN, RST, SCLK, and SEPIN: VIN = VDD1 OSCIN: VIN = VSS VDD1; All outputs open, Xtal: 17.734MHz, LC = 7MHz VDD2; VDD2 = 5.0 V -1 10 15 3.5 1.0 1 Conditions Ratings min typ max 10 Unit A V V A A mA mA
Operating current drain
No. 5396-2/15
LC74751 Timing Characteristics at Ta = -30 to +70C, VDD1 = 50.5 V
Parameter Symbol tW(SCLK) tW(CS) tSU(CS) tSU(SIN) th(CS) th(SIN) tword twt SCLK CS (the period when CS is high) CS SIN CS SIN The time to write 16 bits of data The time to write data to RAM Conditions Ratings min 200 1 200 200 2 200 10 1 typ max Unit ns s ns ns s ns s s
Minimum input pulse width
Data setup time
Data hold time
One-word write time
Serial Data Input Timing
No. 5396-3/15
LC74751 Pin Functions
Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin VSS XtalIN XtalOUT TEST RST SCLK SIN CS LVBK LVCHA VDD2 CVOUT NC CVIN VDD1 SYNIN SEPC SEPOUT SEPIN OSCOUT OSCIN VDD1 Video signal input Power supply Sync separator circuit input Sync separator circuit adjustment Composite sync signal output Vertical synchronizing signal input LC oscillator Power supply (+5 V) Function Ground Crystal oscillator Test output Reset input Clock input Data input Enable input Blanking level adjustment input Character level adjustment input Power supply Video signal output Ground (digital system ground) Connections for the crystal and capacitors used to form the crystal oscillator for generating internal synchronizing signals. Test data output System reset input (This input has hysteresis characteristics.) Clock input for the serial data input function (This input has hysteresis characteristics.) Serial data input (This input has hysteresis characteristics.) Data is input in 16-bit units. Serial data input enable input (This input has hysteresis characteristics.) Serial data input is enabled when this pin is low. Level input signal used to adjust the blanking level. Level input signal used to adjust the character level. Composite video signal adjustment power supply (analog system power supply) Composite video signal output This pin must be either connected to ground or left open. Composite video signal input Power supply (+5 V) Input to the composite sync signal sync separator circuit Sync separator circuit adjustment Sync separator circuit composite sync signal output Connect an integration circuit between the SEPOUT pin and this pin, which inputs the vertical synchronizing signal, to integrate the output signal from the SEPOUT pin. Connections for the coil and capacitor that form the oscillator used to generate the character output dot clock. Power supply (+5 V) Notes
No. 5396-4/15
LC74751 System Block Diagram
Display Screen Structure The display mode has a 24-character by 12-row format. The maximum number of characters that can be displayed is 288. When character sizes are enlarged, the maximum number of characters that can be displayed is reduced. Display ROM (12-line specification) and display RAM (for 176 characters) * Specify fixed characters in the display line ROM. * Application programs use the display RAM to specify characters for sections of the display in which the characters change.
No. 5396-5/15
LC74751 Memory Organization (display RAM and control RAM) Both memory addresses and data are 16-bit quantities. The locations at addresses 000 (000 hexadecimal) to 175 (0AF hexadecimal) hold display memory (RAM) data. The locations at addresses 176 (0B0 hexadecimal) to 191 (0BF hexadecimal) hold display control register data.
Bit Address 000 (000h) DA F 0 DA E 0 DA D 0 DA C 0 DA B 0 DA A 0 DA 9 0 DA 8 0 DA 7 ATTR DA 6 C6 DA 5 C5 DA 4 C4 DA 3 C3 DA 2 C2 DA 1 C1 DA Notes 0 C0
ATTR 175 (0AFh) 176 (0B0h) 177 (0B1h) 178 (0B2h) 179 (0B3h) 180 (0B4h) 181 (0B5h) 182 (0B6h) 183 (0B7h) 184 (0B8h) 185 (0B9h) 186 (0BAh) 187 (0BBh) 188 (0BCh) 189 (0BDh) 190 (0BEh) 191 (0BFh)
Character code
Display RAM
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 HSZ 31 VSZ 31 INT/ NON TST MOD
0 ADR A ADR A ADR A ADR A ADR A ADR A ADR A ADR A ADR A ADR A ADR A ADR A HSZ 30 VSZ 30 LC/ XTAL VSN SEP
0 ADR 9 ADR 9 ADR 9 ADR 9 ADR 9 ADR 9 ADR 9 ADR 9 ADR 9 ADR 9 ADR 9 ADR 9 HSZ 21 VSZ 21 2fsc/ 4fsc 0
0 ADR 8 ADR 8 ADR 8 ADR 8 ADR 8 ADR 8 ADR 8 ADR 8 ADR 8 ADR 8 ADR 8 ADR 8 HSZ 20 VSZ 20 OSC STP BLK 1
ATTR ADR 7 ADR 7 ADR 7 ADR 7 ADR 7 ADR 7 ADR 7 ADR 7 ADR 7 ADR 7 ADR 7 ADR 7 HSZ 11 VSZ 11 DSP ON BLK 0
C6 ADR 6 ADR 6 ADR 6 ADR 6 ADR 6 ADR 6 ADR 6 ADR 6 ADR 6 ADR 6 ADR 6 ADR 6 HSZ 10 VSZ 10 MUTE RVS ON
C5 ADR 5 ADR 5 ADR 5 ADR 5 ADR 5 ADR 5 ADR 5 ADR 5 ADR 5 ADR 5 ADR 5 ADR 5 HP5 VP5 SYS RST
C4 ADR 4 ADR 4 ADR 4 ADR 4 ADR 4 ADR 4 ADR 4 ADR 4 ADR 4 ADR 4 ADR 4 ADR 4 HP4 VP4 SIG MD1
C3 ADR 3 ADR 3 ADR 3 ADR 3 ADR 3 ADR 3 ADR 3 ADR 3 ADR 3 ADR 3 ADR 3 ADR 3 HP3 VP3
C2 ADR 2 ADR 2 ADR 2 ADR 2 ADR 2 ADR 2 ADR 2 ADR 2 ADR 2 ADR 2 ADR 2 ADR 2 HP2 VP2
C1 ADR 1 ADR 1 ADR 1 ADR 1 ADR 1 ADR 1 ADR 1 ADR 1 ADR 1 ADR 1 ADR 1 ADR 1 HP1 VP1
C0 ADR 0 ADR 0 ADR 0 ADR 0 ADR 0 ADR 0 ADR 0 ADR 0 ADR 0 ADR 0 ADR 0 ADR 0 HP0 VP0 Display line ROM specification First character in the first line Display line ROM specification First character in the second line Display line ROM specification First character in the third line Display line ROM specification First character in the fourth line Display line ROM specification First character in the fifth line Display line ROM specification First character in the sixth line Display line ROM specification First character in the seventh line Display line ROM specification First character in the eighth line Display line ROM specification First character in the ninth line Display line ROM specification First character in the tenth line Display line ROM specification First character in the eleventh line Display line ROM specification First character in the twelfth line Horizontal display position Horizontal character size Vertical display position Vertical character size
SIG PHASE PHASE PHASE Video signal and other items MD0 2 1 0 EXT/ INT CBOFF BCOL Control register
BLINK BLINK BLINK 2 1 0
No. 5396-6/15
LC74751 Address 188 (0BC hexadecimal)
DA 0 to C 0 Contents Register HP0 (LSB) Notes State 0 1 0 1 HP1 1 0 2 HP2 1 0 3 HP3 1 0 4 HP4 1 5 HP5 (MSB) 0 1 0 6 HSZ10 1 0 7 HSZ11 1 0 8 HSZ20 1 0 9 HSZ21 1 0 A HSZ30 1 0 B HSZ31 1 HSZ10 HSZ11 0 1 HSZ20 HSZ21 0 1 HSZ30 HSZ31 0 1 0 1 Tc/dot 3 Tc/dot 1 2 Tc/dot 4 Tc/dot 0 1 Tc/dot 3 Tc/dot 1 2 Tc/dot 4 Tc/dot The horizontal character size for lines 2 through 12 0 1 Tc/dot 3 Tc/dot 1 2 Tc/dot 4 Tc/dot The horizontal character size for line 2 The horizontal character size for line 1 Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating mode. Function If HS is the horizontal start position then: HS = Tc x (4 2n HPn)
n=0 5
The 6 bits HP5:0 specify the horizontal display start position. The weight of the low order bit is 4*Tc.
Note: The states of all registers are set to zero when the IC is reset by the RST pin.
No. 5396-7/15
LC74751 Address 189 (0BD hexadecimal)
DA 0 to C 0 Contents Register VP0 (LSB) Notes State 0 1 0 1 VP1 1 0 2 VP2 1 0 3 VP3 1 0 4 VP4 1 5 VP5 (MSB) 0 1 0 6 VSZ10 1 0 7 VSZ11 1 0 8 VSZ20 1 0 9 VSZ21 1 0 A VSZ30 1 0 B VSZ31 1 VSZ10 VSZ11 0 1 VSZ20 VSZ21 0 1 VSZ30 VSZ31 0 1 0 1 H/dot 3 H/dot 1 2 H/dot 4 H/dot 0 1 H/dot 3 H/dot 1 2 H/dot 4 H/dot The vertical character size for lines 3 through 12 0 1 H/dot 3 H/dot 1 2 H/dot 4 H/dot The vertical character size for line 2 The vertical character size for line 1 H: the horizontal synchronization pulse period Function If VS is the vertical display start position then: VS = H x (4 2n VPn)
n=0 5
The 6 bits VP5:0 specify the vertical display start position. The weight of the low order bit is 4*H.
Note: The states of all registers are set to zero when the IC is reset by the RST pin.
No. 5396-8/15
LC74751 Address 190 (0BE hexadecimal)
DA 0 to C Contents Register Notes State 0 0 PHASE0 1 0 1 PHASE1 1 0 2 PHASE2 1 0 3 SIGMD0 1 0 4 SIGMD1 1 0 5 SYSRST 1 0 6 MUTE 1 0 7 DSPON 1 0 8 OSCSTP 1 9 2fsc/ 4fsc/ LC/ XTAL INT/ NON 0 1 0 1 0 1 Stops the crystal oscillator and LC oscillator circuits. Clock frequency: 2fsc Clock frequency: 4fsc The LC oscillator is used for the dot clock. The crystal oscillator is used for the dot clock. Interlaced (262.5 H per field: NTSC, 312.5 H per field: PAL) Noninterlaced (263 H per field: NTSC, 313 H per field: PAL) The OSCIN pin must be tied to VDD if the LC oscillator circuit is not used. Switches interlaced and noninterlaced display. Character display on Crystal oscillator and LC oscillator circuits are not stopped. Only valid in external synchronization mode when character display is off. Crystal oscillator circuit frequency CVIN is cut and CVOUT is fixed at the pedestal level. Character display off Resets all registers and turns display off. Normal output SIGMD1 0 0 1 1 SIGMD0 0 1 0 1 Signal format NTSC PAL PAL-M PAL-N
PHASE2 PHASE1 PHASE0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 NTSC /2 3/2 In phase /4 3/4 5/4 7/4
Function Background color The phase of the background color with respect to the color burst signal.
Background color (phase) PAL (PAL-M, N) /2 In phase
+ /2
3/4 /4
+ /4
3/4
The IC is reset by a low level on the CS pin, and the reset state is cleared by a high level on that pin.
A
B
Note: The states of all registers are set to zero when the IC is reset by the RST pin.
No. 5396-9/15
LC74751 Address 191 (0BF hexadecimal)
DA 0 to C 0 Contents Register Notes State 0 BCOL 1 0 1 CBOFF 1 2 EXT/ INT 0 1 0 3 BLINK0 1 0 4 BLINK1 1 0 5 BLINK2 1 0 6 RVSON 1 0 7 BLK0 1 0 8 BLK1 1 0 9 -- 1 0 A VSNSEP 1 0 B TSTMOD 1 Test mode External V input used (SEPIN: pin 19) Internal V separation circuit used Normal operating mode This bit must be set to 0. Selects V input when superimpose mode is used. Reverse video on BLK0 BLK1 0 1 0 Blinking off Frame size 1 Character size Whole area size Changes the blanking size Blinking period: 1.0 s Reverse video off The burst signal is not output when BCOL is high. External synchronization Internal synchronization BLINK0 BLINK1 0 1 Blinking period: 0.5 s 0 Blinking off 50% duty 1 25% duty 75% duty Changes the blinking period. Switches between external and internal sources for the HSYNC and VSYNC signals. Changes the blinking duty ratio. No background color (Only the background level is set) The burst signal is always output. Function Background color provided (only valid in internal synchronization mode)
Note: The states of all registers are set to zero when the IC is reset by the RST pin.
No. 5396-10/15
LC74751 Memory (Display ROM) Organization This memory has addresses ranging from 0 (000 hexadecimal) to 1535 (5FF hexadecimal). Data has 8 bits.
Bit Address 000 (000h) DA F 0 DA E 0 DA D 0 DA C 0 DA B 0 DA A 0 DA 9 0 DA 8 0 DA 7 ROM/ RAM DA 6 ADR6 DA 5 ADR5 DA 4 ADR4 DA 3 ADR3 DA 2 ADR2 DA 1 ADR1 DA Notes 0 ADR0 Line ROM: First character in the first line
0023 (017h) 0024 (018h)
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
ROM/ RAM ROM/ RAM
ADR6 ADR6
ADR5 ADR5
ADR4 ADR4
ADR3 ADR3
ADR2 ADR2
ADR1 ADR1
ADR0 ADR0
Line ROM: 24th character in the first line Line ROM: First character in the second line
ROM/ RAM
Character code
1535 (5FFh)
0
0
0
0
0
0
0
0
ROM/ RAM
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
Line ROM: 24th character in the 64th line
DA 0 to 8 0
Contents Register Notes State 0 ADR0 1 0 Function Specifies an address in character ROM. When specifying display control RAM, DA7 must be set to 1 and ADR0 to ADR6 must be set to 0. The address specification range for character ROM is 0 to 127 (7F hexadecimal).
1
ADR1 1 0
2
ADR2 1 0
3
ADR3 1 0
4
ADR4 1 0
5
ADR5 1 0
6
ADR6 1 0 Data is read directly from character ROM. Data is read from character ROM through RAM.
7
ROM/ RAM
1
No. 5396-11/15
LC74751 Display Line ROM: Line Address Table
Line no. Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Line 13 Line 14 Line 15 Line 16 Line 17 Line 18 Line 19 Line 20 Line 21 Line 22 Line 23 Line 24 Line 25 Line 26 Line 27 Line 28 Line 29 Line 30 Line 31 Line 32 Address 000HEX 018HEX 030HEX 048HEX 060HEX 078HEX 090HEX 0A8HEX 0C0HEX 0D8HEX 0F0HEX 108HEX 120HEX 138HEX 150HEX 168HEX 180HEX 198HEX 1B0HEX 1C8HEX 1E0HEX 1F8HEX 210HEX 228HEX 240HEX 258HEX 270HEX 288HEX 2A0HEX 2B8HEX 2D0HEX 2E8HEX (0000) (0024) (0048) (0072) (0096) (0120) (0144) (0168) (0129) (0216) (0240) (0264) (0288) (0312) (0336) (0360) (0384) (0408) (0432) (0456) (0480) (0504) (0528) (0552) (0576) (0600) (0624) (0648) (0672) (0696) (0720) (0744) Line no. Line 33 Line 34 Line 35 Line 36 Line 37 Line 38 Line 39 Line 40 Line 41 Line 42 Line 43 Line 44 Line 45 Line 46 Line 47 Line 48 Line 49 Line 50 Line 51 Line 52 Line 53 Line 54 Line 55 Line 56 Line 57 Line 58 Line 59 Line 60 Line 61 Line 62 Line 63 Line 64 Address 300HEX 318HEX 330HEX 348HEX 360HEX 378HEX 390HEX 3A8HEX 3C0HEX 3D8HEX 3F0HEX 408HEX 420HEX 438HEX 450HEX 468HEX 480HEX 498HEX 4B0HEX 4C8HEX 4E0HEX 4F8HEX 510HEX 528HEX 540HEX 558HEX 570HEX 588HEX 5A0HEX 5B8HEX 5D0HEX 5E8HEX (0768) (0792) (0816) (0840) (0864) (0888) (0912) (0936) (0960) (0984) (1008) (1032) (1056) (1080) (1104) (1128) (1152) (1176) (1200) (1224) (1248) (1272) (1296) (1320) (1344) (1368) (1392) (1416) (1440) (1464) (1488) (1512)
No. 5396-12/15
LC74751 Display Screen Structure (Display Example) Specify the display of line 12 for display line ROM (64 lines). From within line ROM, specify display control RAM for the sections where the characters are variable. The addresses in display control RAM are automatically allocated in display order from 0 to 175 (AF hexadecimal). Items enclosed in thick lines specify characters in display control RAM, and items enclosed in thin lines are character specified in line ROM.
Control Data External Input Timing Data is input in a 16-bit serial format that includes both an address and data items. xAn address has 16 bits. The lower 8 bits are the valid address bits. The upper 8 bits must be set to 0. yData consists of 16 bits. * For addresses 000 to 0AF (hexadecimal) the lower 8 bits are valid data. The upper 8 bits must be set to 0. * For addresses 0B0 to 0BB (hexadecimal) the lower 11 bits are valid data. The upper 5 bits must be set to 0. * For addresses 0BC to 0BF (hexadecimal) the lower 12 bits are valid data. The upper 4 bits must be set to 0. zWhen data is input, the first 16 bits after the fall of the CS signal are acquired as the address, and then data is acquired in 16-bit units. The address is automatically incremented ever 16 bits.
No. 5396-13/15
LC74751 Composite Video Signal Output Levels (Internally Generated Levels)
CVOUT output level waveform (VDD2 = 5.00 V)
Output level VCHA: Character VRSH: Background color high VCBH: Color burst high VRSL: Background color low VBK: Frame VPD: Pedestal level VCBL: Color burst low VSN: Sync
Output voltage (1) (VDC) 2.650 2.075 1.700 1.500 1.500 1.375 1.050 0.800
Output voltage (2) (VDC) 2.875 2.275 1.900 1.700 1.700 1.575 1.250 1.000
VDD2 = 5.000VDC
No. 5396-14/15
LC74751 Application Circuit Example
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1996. Specifications and information herein are subject to change without notice. No. 5396-15/15

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